1. Field of the Invention
The present invention relates generally to a charge transfer apparatus and a driving method of the apparatus. In particular, the invention relates to a two-phase driving-type charge transfer apparatus suitable for use as horizontal transfer registers of a CCD area sensor, transfer registers of a CCD linear sensor, and transfer registers of a CCD delay device. The invention also relates to a driving method of the above type of charge transfer apparatus.
2. Description of the Related Art
The following driving method is mainly employed in a two-phase driving-type CCD charge transfer apparatus. As shown in FIG. 7, a predetermined DC-bias potential E is applied to a gate electrode 74 of an output gate section 73 through which signal charges are transferred from the final stage (.phi.H1) of a charge transfer section 71 to a charge detecting section 72. This method is advantageous in that the application of DC bias to the gate electrode 74 of the output gate section 73 reduces the level of "coupling" caused by clock driving. "Coupling" refers to fluctuations of a waveform due to capacitive coupling caused by a parasitic capacitor between the gate electrode 74 of the output gate section 73 and the floating region of the charge detecting section 72.
The charge transfers apparatus of the above type of which DC bias is applied to the gate electrode 74 of the output gate section 73, on one hand, has the advantage of reducing the level of coupling to the output waveform, but on the other hand, presents the following problem. The potential of the output gate section 73 is fixed. This decreases, as shown in FIG. 8, the transfer potential difference A.DELTA..phi.1 between the final stage of the charge transfer section 71 and the output gate section 73 to one half of the amplitude of each of the transfer clocks .phi.H1 and .phi.H2 of the charge transfer section 71 or even smaller, the potential difference .DELTA..phi.1 determining the amount of charge to be handled in the final stage of the charge transfer section 71, thereby easily decreasing the transfer efficiency of the output gate section 73.
For solving this problem, the following type of charge transfer apparatus is known, as disclosed in Japanese Patent Laid-Open No. 6- 78220 the apparatus in which the transfer clock for driving the stage one prior to the final stage of the charge transfer section is differentiated, and the resulting differential waveform is applied to the gate electrode of the output gate section. That is, as indicated by the construction of the apparatus shown in FIG. 9, transfer clock .phi.H2 for driving the stage one prior to the final stage of a charge transfer section 91 is differentiated by a CR differentiating circuit 92, and an output gate section 93 is driven by the resulting differential waveform.
With this construction, the differential waveform is applied to an output electrode 94 while signal charges are transferred from the final stage of the charge transfer section 91 to a charge detecting section 95 via the output gate section 93. This temporarily increases the potential of the output gate section 93, during which the transfer potential difference A.DELTA..phi.between the final stage of the charge transfer section 91 and the output gate section 93 becomes larger, thus enhancing the transfer efficiency of the output gate section 93.
However, the conventional charge transfer apparatus constructed as described above encounters the following problems. Transfer clock .phi.H2 is differentiated and then applied to the gate electrode 94 of the output gate section 93. The transfer potential difference .DELTA..phi.1 can thus be temporarily increased only during this differentiating period, which is insufficient for the transfer period. Additionally, there presents no problem at all if the phases of two-phase transfer clocks .phi.H1 and .phi.H2 are completely reversed to each other, as indicated by the solid lines shown in FIG. 10. If transfer clock .phi.H2 is, however, out of phase as indicated by the broken line shown in FIG. 10, after the differential waveforms has disappeared, transfer clock .phi.H1 is changed to the "L" level, and transfer clock .phi.H2 is changed to the "H" level. In this state, the transfer operation of signal charges from the final stage of the charge transfer section 91 to the charge detecting section 95 is started. Thus, the foregoing advantages cannot be obtained.